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Energy-Efficient RISC-V Processors in 28nm FDSOI

Broivoje Nikolic

This talk presents the design of a series of energy-efficient microprocessors done by a group of students at UC Berkeley. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling, with high energy efficiency the designs feature an integrated switched-capacitor DC-DC converter and direct power measurement, with an integrated power-management unit. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.

Speaker: Borivoje Nikolic, UC Berkeley

Tuesday, 11/14/17


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Santa Clara Valley IEEE Computer Society

Cadence, Bldg 10
2655 Seely Ave
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