RISC-V Instruction Set Architecture has recently become a key driver for driving open source projects across wide gamut of end applications. Most recently we have seen a lot of application in the Internet of Things (IoT) segment, microcontrollers for a variety of traditional embedded applications, and applications requiring capability for low power operation of inference engines based on artificial neural networks.
We have developed a super-scalar (2-way), 9-stage pipeline, mostly in-order, open-source core based on the RISC-V RV32IMC instructions set, named SweRV. It initially targets in-house embedded Storage System on Chip applications. We present some of the architectural details of the core and implementation challenges, as well as discuss application of the core for the Flash controllers. We also report performance measurements of Coremark and Dhrystone benchmarks, which are traditionally used for embedded core performance benchmarking. Some of the implementation challenges that we have encountered were related to the tradeoff of code density and performance of RISC-V. We report our initial findings and code density improvement solutions based on compiler and linker optimizations.
We are witnessing computation shifting to dedicated machine learning and inference accelerators, typically attached to high speed peripherals buses (PCI express, OpenCAPI) or smart networking protocols (OmniXtend). These systems are typically implemented by high density arrays of multiple and accumulate (MAC) elements. Some of implementations are based on RISC-V Cores implementing vector instruction set extensions. We will review vector set instructions in RISC-V and highlight the architectural value for machine learning and neural network inferencing workloads.
Speaker: Zvonimir Bandic, Western Digital
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