Inter-Chiplet Synchronization of Multi-Die VLSI Systems - Livestream

In VLSI systems, computing is projected to contain hundreds of components from heterogeneous processors, memories, and interconnect, in order to achieve performance gains and energy-efficiency in the face of increasing power-density. However, both hardware and software designers are faced with limitations in the improvement of instructions-per-cycle and clock frequency. As a result, designers have sought out heterogeneous computing devices, in system architecture and VLSI packaging, to accelerate current and future workloads. At the VLSI packaging level, silicon interposer based heterogeneous integration of multi-die systems has provided a new avenue for scaling of in-package computation, memory, and interconnects.

This talk will focus on the synchronization subset of our efforts for silicon interposer based integration of multi-die VLSI systems. In particular, a solution developed for inter-die synchronization in MDS that has a resonant clocking technology backbone. Resonant clocking technologies, which work on adiabatic, charge-recycling switching principles, generate very high frequency clock signals at a low power dissipation rate. In MDS, the presented implementation has a minimum footprint on the active interposer, which is important for yield and cost. The proposed solution provides a centralized, synchronized and lightweight clock generation and delivery system that eliminates the need for PLLs and various clock/phase correction/synchronization overhead, which could especially be prohibitive for large scale MDS systems. In addition to a superior synchronization profile, the proposed resonant clocking delivery leads to an average of ~40% total chiplet power savings (~72% on the clock network) in comparison to PLL-synchronized ARM Cortex M0-based 10mm by 12mm multi-core MDS simulation model. This talk will also highlight two specific solutions developed for increased heterogeneity in architectures (and their efficiency) using resonant-clocking based inter-chipset synchronization, where these architectures 1) demand frequency/voltage points distributed both spatially and temporally to achieve optimal performance, 2) require efficient I/O interface between chiplets.

Speaker: Baris Taskin, Drexel University

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