SPARC 3.6 GHz Processor: a 16-core, 1024 threaded SoC
Jason Hart received the B.S. degree in electrical engineering from the University of Idaho, Moscow. He joined Sun Microsystems, Inc. in 1995 after working in Product Engineering at Micron Technology, Boise, ID. Jason has been doing circuit design, global circuits and composition for UltraSPARC I, III, IV+ and now Oracle's T5. Design work has included SRAM's, register files, static and dynamic custom circuits, libraries, timing, FGU composition, and responsibility for clocking on T5.
Tuesday, 08/13/13
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Santa Clara Valley IEEE Computer Society
Cadence, Bldg 10
2655 Seely Ave
San Jose, CA 95134
2655 Seely Ave
San Jose, CA 95134
Website: Click to Visit
