Shannon-inspired Statistical Computing

Moore's Law has been the driving force behind the exponential growth in the semiconductor industry for the past five decades years. Today, energy efficiency and reliability challenges in nanoscale CMOS (and beyond CMOS) processes threaten the continuation of Moore's Law. This talk will describe our work on developing a Shannon-inspired statistical information processing that seeks to address this issue by treating the problem of computing on unreliable devices and circuits as one of information transfer over an unreliable/noisy channel. Such a paradigm seeks to transform computing from its von Neumann roots in data processing to Shannon-inspired information processing. Key elements of this paradigm are the use of statistical signal processing, machine learning principles, equalization and error-control, for designing error-resilient on-chip computation, communication, storage, and mixed-signal analog front-ends. The talk will provide a historical perspective and demonstrate examples of Shannon-inspired designs of on-chip subsystems. This talk will conclude with a brief overview of the Systems On Nanoscale Information fabriCs (SONIC) Center, a multi-university research center based at the University of Illinois at Urbana-Champaign, focused on developing a Shannon/brain-inspired foundation for information processing on CMOS and beyond CMOS nanoscale fabrics.

Speaker: Naresh Shanbhag, Univ. of Illinois, Urbana-Champaign