Bleeding Edge FPGA and Digital Design: New Challenges At High Gigabit Rates

Today's ASICs and FPGAs include multi-gigabit data transceivers that operate at 28 Gigabits per second. Future 56 Gigabit per second links are being designed and will arrive soon. Problems have been encountered in making these new data links eliable. The physics of PC Board signal transmission at these rates is the next high frequency challenge for digital and signal integrity engineers. This presentation investigates these latest challenges and some of the proposed solutions.

Speaker: Chuck Corley, National Instruments