Top SoC Design Challenges – Panel
This talk features a panel of leading experts discussing the top challenges of SoC design in today's competitive world. Hans Spanjaart will be the moderator for the discussions.
Panel: Naresh Sehgal, Intel, SW Director for FPGA based Silicon platforms for Mobile products
Paul McLellan, SemiWiki Project, Blogger & EDA Expert
Tom Dillinger, Oracle, CAD Technology
John Swan, Swan on Chips, SoC Technologist
Tuesday, 04/08/14
Contact:
Website: Click to VisitCost:
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Santa Clara Valley IEEE Computer Society
Cadence, Bldg 10
2655 Seely Ave
San Jose, CA 95134
2655 Seely Ave
San Jose, CA 95134
Website: Click to Visit
