Computer Technology Basics: Past, Present, and Future

The speaker will propose a new approach to CPU architecture design, when only the algorithm and data dependency would limit the theoretical speed of execution. This algorithm centric architecture brings a new level of power efficiency and dynamic range, which leads to a new post-superscalar CPU era.

A detailed historical analysis of how CPU architecture has been developed during the past 60 years, why we see stagnation in CPU architecture now, and as the result of such analysis – if there is a way out of this crisis in processor architecture.

This critical analysis of the basic features of computer technology (High Level Language, processor architecture, OS kernel and compiler) will be performed in two orthogonal dimensions

Functionality of primitive data types and corresponding operations (space component)The way how these operations are executed in time – parallelism (time component)
The way how these operations are executed in time – parallelism (time component)

The most significant steps, taken in this area in the past, will be discussed.

Possible future steps in both above mentioned components (functionality and parallelism) are suggested, which allows reaching practical results close to the best possible ones for two cases:

For architecture semantically fully compatible with existing architectures (ARM, x86, POWER, etc.) – post superscalar architecture
For computer technology, which is free of any compatibility constraints

In the first case we estimate 3x – 4x higher Single Thread performance over the best current superscalar CPUs and two times for MT performance (for the same area) over existing architectures with better power efficiency and decreased design complexity.

For the second case we can predict the following advantages:

Result of the functional (space component) improvements

Have been implemented the in Russian widely used Elbrus-1, -2 computers

Architecture support for real High Level programming
SW debugging is about 10 times easier
Complete solution of security protection problem
Clean (and about 4x times smaller) OS kernel with user level programming – no need for privileged mode

Result of parallel execution (time component) improvement
Possibility to use all available HW (about 60 clusters) even for Single Thread jobs
Parallel execution of procedures
Dramatic increase in performance – both ST and MT
General result

Due to ability to use all available HW and the fact that the performance results are close to algorithmic constraint, this computer technology will be really absolutely universal among the programmable architectures.

The following result should be investigated more carefully, however, there is a big probability that it can support well all applications, which currently require specialized equipment like:

Graphics
Machine learning
Computer vision
Etc.

Speaker: Boris Babayan, Intel